1. Field of the Invention
The present invention relates to the field of MOS integrated circuits and, particularly to the process of forming source and drain regions of a CMOS integrated circuit device.
2. Prior Art
In the design of integrated circuits various processes are known for fabricating the actual device. Techniques have evolved over the years in which various layers are formed onto a silicon substrate, wherein these layers are subjected to one or more of a variety of photolithographic, patterning, etching, exposing, implanting steps, etc., in order to form the desired device One type of integrated circuit is a metal-oxide semiconductor (MOS) field-effect transistor (FET) in which source and drain regions of the transistor are separated by a channel region underlying the gate of the transistor. Where the transistor is formed on the substrate, source and drain regions are formed in the substrate and the gate region resides above the surface of the substrate.
Typically the source and drain regions are formed by doping the substrate in the area where these regions are to be formed. Ion implantation is one technique for doping the source and drain. Using gate alignment, the gate or the gate and an adjacent dielectric spacer are used to align the substrate area where the doping is to occur. A well known practice is to provide a first implant to define a first implanted area and a second implant to define a second implanted area. The second implanted area is the actual source or drain and the first implanted area provides a graded doping or lightly doped region between the source or the drain from the channel, in order to provide improved device integrity, especially higher breakdown drain voltages.
Although these techniques are well-known, the various specific processes are applicable for fabricating devices of a certain size. As device geometry shrinks, attempts are made to form more and more transistors on a given area of a semiconductor wafer. For example, a semiconductor device fabricated utilizing "submicron" technology will contain many more circuit elements per unit area than a device fabricated using "above-micron" technology. However, as device size continues to shrink, the dimensional tolerances required of the various formed layers and/or devices also shrink and become more critical. Thus tolerances adequate for forming source and drain regions for a given size device, such as a device fabricated using 1.5 micron technology, may be inadequate for improved devices, such as a device fabricated using 0.35, 0.5 or even 0.8 micron technology.
The present invention provides for an improved method of forming source and drain regions in a semiconductor device, wherein the sharper definition, such as tighter control of source-drain spacing and source and drain doping profiles, of these regions permit for the fabrication of devices using submicron technology. Further, the improved method also provides for an ease of manufacture in fabricating the device.